Formal Verification of Synchronization schemes in Clock Domain Crossing:
(Atrenta India Pvt. Ltd., July 2006-present)
Among the many verification challenges confronting system-on-chip (SOC) designers these days, clock domain crossings (CDCs) rank very high in difficulty. The latest SOCs may have dozens or even thousands of clock domains, many of them difficult to verify using conventional tools such as simulation. For these bugs to be detected in simulation it requires long simulation runs and a chance encounter. As a consequence, CDCs have become a leading cause of design errors. The project involves detection of such clock domain crossings. My work has been in formal verification of functional correctness of synchronization schemes (two flop, common mux, mux-lock and user defined synchronizers). These checks form a part of Spyglass-CDC tool.
B.Tech project:Design of Optimal Signal Classifiers (B.Tech. Thesis)
(Supervisor: Prof. A. Routray, Indian Institute of Technology)
[The thesis aimed at design of optimal signal classifiers and extraction of best feature set for classification of non-stationary signals.
a)Partition of auto-correlation space using Singular value decomposition has also been proposed for obtaining the features of a signal. To improve its performance , linear matrix inequality(LMI) embedding (approximating using Convex Optimization) has been used for auto-correlation sequence estimation.
b)Moreover, we have proposed the use of time-frequency representation(TFR) for classification of non-stationary signals since they are able to detect disturbance in signal along with their localization in time. Further, Stochastic Genetic Algorithm based joint Optimization for finding optimal TFR parameters and Support Vector Machine parameters has been proposed.
c) Emotion classification using speech]
Design of an Experiential Sampling based Robust Blob Detector for Multimedia Surveillance (May - July 2005)
(Internship at School of Computing ,National University of Singapore. Mentor : Prof. Mohan .S. Kankanhalli)
The project concentrated on a part of the newly designed framework for multimedia surveillance which dealt with Foreground/Background segmentation in a given video stream. To be more precise it aimed to design a robust and fast algorithm to detect the foreground in a given frame of video. An Experiential Sampling (for speed) based blob detector was designed which modeled each pixel of the image by a mixture of Gaussians (for robustness). The work has been presented at International Conference of Multimedia and Expo (ICME), 2006 under the title "Experiential Sampling Based Foreground/Background Segmentation for Video Surveillance".
Event Detection and Classification in Video Stream for Multimedia Surveillance (May - July 2005)
(Internship at School of Computing ,National University of Singapore. Mentor : Prof. Mohan .S. Kankanhalli)
The project aimed at the detection and classification of human activities for multimedia surveillance application. The implemented algorithm was able to classify the various human activities in a corridor like walking ,running ,standing or a combination of these micro events forming a macro event .It also did a color analysis of the foreground to satisfy user query like " Is there anybody who has passed through this corridor wearing red shirt and black trouser?".
Work on this project has been presented in the 3rd ACM International Workshop on Video Surveillance & Sensor Networks,Singapore-2005- "Timeline-based Information Assimilation multimedia Surveillance and Monitoring Systems".
Verilog Implementation of second order Kalman Filter ( Apr. 2005)
(Mentor : Prof. A. Routray, Electrical Engineering, Indian Institute of Technology)
The implemented filter aimed at estimating the parameters of a digital signal. The implementation was done on Verilog with LMS algorithm used for error minimization. The algorithm helped in fairly accurate estimation of signals of low frequency (like high power signals).
